In general, a semiconductor memory device is supplied with a power supply voltage (VDD) and a ground voltage (VSS) from an outside source, and generates and uses internal voltages which are necessary for internal operations. Voltages necessary for internal operations of a memory device include a core voltage (VCORE) supplied to a memory core region, a boosted voltage (VPP) used for driving or overdriving of a word line, and a reduced voltage (VBBW) supplied as a bulk voltage of a MOS transistor.
While the core voltage (VCORE) may be supplied by reducing a power supply voltage (VDD) inputted from an outside source to a predetermined level, because the boosted voltage (VPP) is a voltage with a higher level than the power supply voltage (VDD) inputted from the outside source and the reduced voltage (VBBW) is a voltage with a lower level than the ground voltage (VSS), a charge pump circuit is needed to supply charges to the boosted voltage (VPP) and the reduced voltage (VBBW).
As a semiconductor memory device trends toward high integration and high capacity, the thickness of a MOS transistor and the thickness of a gate oxide layer (SiO2) gradually decrease. On the contrary, since a boosted voltage (VPP) is still maintained high, the intensity of an electric field which is applied to the gate of a MOS transistor using the boosted voltage (VPP) is substantial. Accordingly, in a MOS transistor, GIDL (gate induced drain leakage) gradually increases which typically causes characteristics and productivity of the semiconductor memory device to deteriorate.
FIG. 1 is a circuit diagram of a conventional buffer circuit.
Referring to FIG. 1, the conventional buffer circuit includes a PMOS transistor P100 configured to pull-up drive a node nd100, from which an output signal OUT is outputted, with a boosted voltage VPP in response to an input signal IN. The conventional buffer circuit also includes an NMOS transistor N100 configured to pull-down drive the node nd100 with a reduced voltage VBBW in response to the input signal IN.
Operations of the conventional buffer circuit configured in this way will be described with reference to FIG. 2, by being divided into a standby mode in which the input signal IN is applied as the reduced voltage VBBW, and an active mode in which the input signal IN is applied as the boosted voltage VPP.
In the standby mode, the PMOS transistor P100 is turned on by the input signal IN applied as the reduced voltage VBBW, and the node nd100 is pull-up driven by the boosted voltage VPP. Accordingly, a voltage difference VDG between the drain and the gate of the NMOS transistor N100, which is turned off, is induced largely by the difference between the boosted voltage VPP and the reduced voltage VBBW. For example, when a semiconductor memory device in which the reduced voltage VBBW is set to −0.2V and the boosted voltage VPP is set to 2.9V, the voltage difference between the drain and the gate of the NMOS transistor N100 reaches 3.1V. Therefore, an amount of leakage current in the NMOS transistor N100 abruptly increases due to GIDL. Also, the voltage difference between the drain and the source of the NMOS transistor N100 increases, which causes an amount of leakage current due to channel-off leakage to increase.
In the active mode, the NMOS transistor N100 is turned on by the input signal IN applied as the boosted voltage VPP, and the node nd100 is pull-down driven by the reduced voltage VBBW. At this time, since the boosted voltage VPP is applied to the gate of the NMOS transistor N100, the NMOS transistor N100 should be formed in such a manner that a gate oxide layer has a thickness larger than a predetermined thickness. As the gate oxide layer of the NMOS transistor N100 is formed to be thicker, an operating speed in the active mode decreases.